1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it relates to a method of manufacturing a MOSFET having salicide structure. The present invention also relates to a method of manufacturing a semiconductor device having a plurality of types of semiconductor elements for different applications formed in a single wafer.
2. Description of the Background Art
Background Art 1
FIGS. 46 to 52 are sectional views showing a conventional method of manufacturing a semiconductor device in step order. In particular, these figures successively illustrate steps of manufacturing a MOSFET having a salicide structure. First, element isolation insulative films 102 consisting of silicon oxide are formed on element isolation regions of a silicon substrate 101, thereafter ion implantation is performed for forming a well, a channel (not shown) and the like, and thereafter a gate oxide film 103 consisting of silicon oxide and a gate electrode 104 consisting of polysilicon are selectively formed on an upper surface of the silicon substrate 101. Thereafter ion implantation is performed for forming impurity regions (hereinafter referred to as extensions) 105 in the upper surface of the silicon substrate 101 (FIG. 46).
Then, a silicon oxide film 106 is deposited on the overall surface by CVD, for example, and thereafter a silicon nitride film 107 is deposited on the silicon oxide film 106 (FIG. 47). Then, the silicon nitride film 107 and the silicon oxide film 106 are etched in this order by anisotropic dry etching having a high etching rate along the depth of the silicon substrate 101, to expose the upper surface of the silicon substrate 101. Thus, side walls 110 defined by silicon oxide films 108 and silicon nitride films 109 are formed on side wall portions of the gate electrode 104 (FIG. 48).
Then, ion implantation is performed through the gate electrode 104 and the side walls 110 serving as masks, to form impurity regions 111 in the exposed upper surface of the silicon substrate 101. Consequently, source/drain regions 112 defined by the extensions 105 and the impurity regions 111 are formed in the upper surface of the silicon substrate 101 (FIG. 49).
Then, silicon is grown under conditions having selectivity for a silicon oxide film and a silicon nitride film (this means crystal growth under such conditions that silicon is grown not on a silicon oxide film and a silicon nitride film but on the remaining region) for forming a silicon growth layer 113 on an upper surface of the gate electrode 104 while forming silicon growth layers 114 on the upper surface of the silicon substrate 101 in portions formed with the impurity regions 111 (FIG. 50).
Then, a cobalt layer 115 is deposited on the overall surface by CVD, for example (FIG. 51), and thereafter heat treatment is performed in an inert gas atmosphere of nitrogen, argon or the like. Thus, the cobalt layer 115 reacts with the silicon growth layers 113 and 114, to form cobalt silicide layers 116 and 117. Thereafter unreacted parts of the cobalt layer 115 are removed (FIG. 52). A MOSFET having a salicide structure is manufactured through the aforementioned steps. Thereafter the device is completed through a process including a step of forming an interlayer insulative film, a wiring step and the like.
Background Art 2
FIGS. 53 to 57 are sectional views showing another method of manufacturing a semiconductor device in step order. In particular, these figures successively illustrate steps of manufacturing a semiconductor device having a plurality of types of semiconductor elements for different applications formed in a single wafer. First, element isolation insulative films 102 consisting of silicon oxide are formed on element isolation regions of a silicon substrate 101, thereafter ion implantation is performed for forming a well, a channel (not shown) and the like, and thereafter gate oxide films 103 consisting of silicon oxide and gate electrodes 104 consisting of polysilicon are selectively formed on an upper surface of the silicon substrate 101. Thereafter ion implantation is performed to form extensions 105 in the upper surface of the silicon substrate 101 (FIG. 53).
Then, a silicon oxide film 106 is deposited on the overall surface by CVD, for example (FIG. 54). Thereafter a silicon nitride film 107 is deposited on the silicon oxide film 106 by CVD, for example (FIG. 55). Thereafter the silicon nitride film 107 and the silicon oxide film 106 are etched in this order by anisotropic dry etching having a high etching rate along the depth of the silicon substrate 101, to expose the upper surface of the silicon substrate 101. Thus, side walls 110a defined by silicon oxide films 108 and silicon nitride films 109 are formed on side wall portions of the gate electrode 104 in a DRAM part of the silicon substrate 101, while side walls 110b defined by silicon oxide films 108 and silicon nitride films 109 are formed on side wall portions of the gate electrode 104 in a logic part of the silicon substrate 101 (FIG. 56).
Then, ion implantation is performed through the gate electrodes 104 and the side walls 110a and 110b serving as masks, to form impurity regions 111 in the exposed upper surface of the silicon substrate 101. Consequently, source/drain regions 112 defined by the extensions 105 and the impurity regions 111 are formed in the upper surface of the silicon substrate 101 (FIG. 57). A DRAM-MOSFET and a logic MOSFET are formed on the DRAM part and the logic part of the silicon substrate 101 respectively through the aforementioned steps. Thereafter the device is completed through a process including a step of forming an interlayer insulative film, a wiring step and the like.
Problem related to Background Art 1
In order to increase the operating speed of a MOSFET or improve the high-frequency characteristic thereof, it is also important to reduce gate resistance and source/drain resistance. While the gate resistance is reduced by forming a conductive layer such as the cobalt silicide layer 116 on the gate electrode 104 as in the MOSFET shown in FIG. 52, the gate resistance can be further reduced if the width of the cobalt silicide layer 116 can be increased.
As shown in FIG. 52, however, the width of the cobalt silicide layer 116 is substantially equal to the gate length in the conventional MOSFET, and hence the gate length must be increased in order to increase the width of the cobalt silicide layer 116. If the width of the gate electrode 104 is increased in order to increase the gate length, however, the source-to-drain distance is also increased. Consequently, the channel resistance is increased to reduce the driving current for the MOSFET, to result not only in reduction of the operating speed and the high-frequency characteristic of the MOSFET but also in insufficient satisfaction of requirement for refinement of the device.
FIGS. 58 and 59 are sectional views showing parts A and B in FIG. 50 in an enlarged manner respectively. As hereinabove described, the silicon growth layer 114 is formed by growing silicon on the upper surface of the silicon substrate 101. At this time, a specific plane orientation influences the growth rate, and hence facets appear on end portions of the silicon growth layer 114. FIG. 58 shows a facet 120a appearing on an end portion of the silicon growth layer 114 closer to the side wall 110, while FIG. 59 shows a facet 120b appearing on an end portion of the silicon growth layer 114 closer to the element isolation insulative film 102. A silicon oxide film 106a shown in FIG. 59 is a part of the silicon oxide film 106, deposited on the element isolation insulative film 102, remaining on the side wall portion of the element isolation insulative film 102 in the anisotropic dry etching for forming the side wall 110.
The end portions of the silicon growth layer 114 are smaller in thickness than the central portion due to the presence of the facets 120a and 120b. Silicification of the silicon growth layer 114 for forming the cobalt silicide layer 117 gradually progresses from the interface between the silicon growth layer 114 and the cobalt layer 115, i.e., from an upper surface of the silicon growth layer 114 along the depth. On the end portions of the silicon growth layer 114 having the smaller thickness, therefore, the cobalt silicide layer 117 is formed up to deep portions of the silicon substrate 101 as compared with the central portion having the larger thickness. Thus, the source/drain region 112 must be previously deeply formed so that the parts of the cobalt silicide layer 117 formed in the deep portions of the silicon substrate 101 do not pass through the source/drain region 112. Thus, the source/drain region 112 cannot be much shallowly formed and hence the device is hard to refine in the conventional method of manufacturing a MOSFET.
Problem of Background Art 2
As shown in FIG. 57, the DRAM-MOSFET and the logic MOSFET are formed on the silicon substrate 101 in a hybrid state. Since the DRAM-MOSFET must have stable electric characteristics, the impurity regions 111 preferably separate from each other to some extent in order to reliably form source and drain regions, in consideration of dispersion in process. On the other hand, the logic MOSFET must have high drivability, and hence the distance between the impurity regions 111 is preferably minimized in order to reduce the respective resistance values of the source and drain regions. Thus, the performance required to the DRAM-MOSFET is different from that required to the logic MOSFET, and hence it is preferable if the distances between the impurity regions 111 can be set in the MOSFETs independently of each other.
As shown in FIG. 57, however, the side walls 110a of the DRAM part are equal in width to the side walls 110b of the logic part in the conventional method of manufacturing a semiconductor device. Therefore, the distances between the impurity regions 111 for the source and drain parts thereafter formed by ion implantation are identical to each other in the DRAM part and the logic part. Thus, the conventional method of manufacturing a semiconductor device cannot satisfy the aforementioned requirement.
According to a first aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) selectively forming a multilayer structure of a gate insulator film and a gate electrode stacked in this order on a main surface of a substrate; (b) forming a side wall consisting of at least first and second materials and having an exposure region exposing the second material between a portion of an upper surface of the side wall exposing the first material and an upper surface of the multilayer structure; and (c) forming a conductive layer extending from the exposure region to the upper surface of the multilayer structure.
According to the first aspect of the present invention, a conductive layer having a larger width than the gate electrode can be formed without increasing the width of the gate electrode, for attaining reduction of gate resistance.
According to a second aspect of the present invention, the side wall consists of the first and second materials and a third material, the upper surface of the side wall has a portion exposing the third material between the exposure region and the upper surface of the multilayer structure, and the step (c) is carried out through the steps of: (c-1) growing a semiconductor from each of the exposure region and the upper surface of the multilayer structure thereby forming a semiconductor growth layer extending from the exposure region to the upper surface of the multilayer structure through growth to the direction of the gate length; and (c-2) forming a semiconductor-metal compound by reaction of the semiconductor growth layer with metal, thereby forming the conductive layer in the method of manufacturing a semiconductor device according to the first aspect of the present invention.
According to the second aspect of the present invention, the semiconductor growth layer extending from the exposure region to the upper surface of the multilayer structure is formed through growth to the direction of the gate length and this semiconductor growth layer reacts with the metal to form the semiconductor-metal compound, whereby a conductive layer having a larger width than the gate electrode can be properly formed.
According to a third aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) selectively forming a multilayer structure of a gate insulator film and a gate electrode film stacked in this order on a main surface of a substrate; (b) forming a side wall consisting of at least first and second materials and having a first region exposing the second material on a side surface of the side wall in the vicinity of the main surface of the substrate; (c) growing a semiconductor from each of the first region and the exposed main surface of the substrate thereby forming a semiconductor growth layer; and (d) forming a semiconductor-metal compound by reaction of the semiconductor growth layer with metal.
According to the third aspect of the present invention, the semiconductor growth layer is formed by growing the semiconductor not only from the exposed main surface of the substrate but also from the first region of the side wall, whereby occurrence of a facet can be avoided on an end portion of the semiconductor growth layer closer to the gate electrode.
According to a fourth aspect of the present invention, the method of manufacturing a semiconductor device according to the third aspect of the present invention further comprises the steps of: (e) forming an element isolation structure having a projecting part at least partially projecting on the main surface of the substrate in an element isolation region of the substrate; and (f) forming a second region consisting of a third material on a side wall portion of the projecting part, both of which are carried out in advance of the step (c), wherein in the step (c), the semiconductor growth layer is formed by growing the semiconductor from each of the first region, the exposed main surface of the substrate and the second region.
According to the fourth aspect of the present invention, the semiconductor growth layer is formed by growing the semiconductor also from the second region formed on the side wall portion of the projecting part of the element isolation structure, whereby occurrence of a facet can be avoided on an end portion of the semiconductor growth layer closer to the element isolation structure.
According to a fifth aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) selectively forming a multilayer structure of a gate insulator film and a gate electrode stacked in this order on a main surface of a substrate; (b) forming a side wall consisting of at least first and second materials and having a first region exposing the second material between a portion of an upper surface of the side wall exposing the first material and an upper surface of the multilayer structure while having a second region exposing the second material on a side surface of the side wall in the vicinity of the main surface of the substrate; (c) growing a semiconductor from each of the first region and the upper surface of the multilayer structure for forming a first semiconductor growth layer extending from the first region to the upper surface of the multilayer structure through growth to the direction of the gate length while growing a semiconductor from each of the second region and the exposed main surface of the substrate thereby forming a second semiconductor growth layer; and (d) forming semiconductor-metal compounds by reaction of the first and second semiconductor growth layers with metal.
According to the fifth aspect of the present invention, gate resistance can be reduced without increasing the width of the gate electrode in relation to the semiconductor device having a salicide structure, while occurrence of a facet can be avoided on an end portion of the second semiconductor growth layer closer to the gate electrode.
According to a sixth aspect of the present invention, the method of manufacturing a semiconductor device according to the fifth aspect of the present invention further comprises the steps of: (e) forming an element isolation structure having a projecting part at least partially projecting on the main surface of the substrate on an element isolation region of the substrate; and (f) forming a third region consisting of a third material on a side wall portion of the projecting part, both of which are carried out in advance of the step (c), wherein in the step (c), the second semiconductor growth layer is formed by growing a semiconductor from each of the second region, the exposed main surface of the substrate and the third region.
According to the sixth aspect of the present invention, gate resistance can be reduced without increasing the width of the gate electrode in relation to the semiconductor device having a salicide structure, while occurrence of a facet can be avoided on an end portion of the second semiconductor growth layer closer to the gate electrode and occurrence of a facet can be avoided also on the end portion of the second semiconductor growth layer closer to the element isolation structure.
According to a seventh aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) employing a substrate having a first element forming region for forming a first semiconductor element and a second element forming region for forming a second semiconductor element, to form a first multilayer structure of a gate insulator film and a gate electrode stacked in this order on a main surface of the substrate in the first element forming region and to form a second multilayer structure of a gate insulator film and a gate electrode stacked in this order on a main surface of the substrate in the second element forming region; (b) forming a first side wall having a first width on a side wall portion of the first multilayer structure; (c) forming a second side wall having a second width different from the first width on a side wall portion of the second multilayer structure; and (d) implanting an impurity into the main surface of the substrate through the first and second multilayer structures and the first and second side walls serving as masks thereby forming paired first impurity implantation regions in the main surface of the substrate in the first element forming region and paired second impurity introduction regions in the main surface of the substrate in the second element forming region.
According to the seventh aspect of the present invention, the first and second impurity implantation regions are formed by implanting the impurity through the first and second multilayer structures and the first and second side walls serving as masks respectively, while the widths of the first and second side walls are different from each other. Therefore, the distance between the paired first impurity implantation regions and that between the paired second impurity implantation regions can be set independently of each other in response to the respective applications of the first and second semiconductor elements.
According to an eighth aspect of the present invention, the first side wall consisting of at least first and second materials and having an exposure region exposing the second material between a portion of an upper surface of the side wall exposing the first material and an upper surface of the first multilayer structure is formed in the step (b) in the method of manufacturing a semiconductor device according to the seventh aspect of the present invention, and the method of manufacturing a semiconductor device further comprises the step of: (e) forming a conductive layer extending from the exposure region to the upper surface of the first multilayer structure.
According to the eighth aspect of the present invention, gate resistance of the first semiconductor element can be reduced without increasing the width of the gate electrode in the first multilayer structure.
According to a ninth aspect of the present invention, in the step (c), the side wall is formed through the steps of: (c-1) forming the first side wall on a side wall portion of the second multilayer structure; and (c-2) removing the first material from the first side wall in the method of manufacturing a semiconductor device according to the eighth aspect of the present invention.
According to the ninth aspect of the present invention, the second side wall having a width shorter than the first side wall by that of the first material can be formed on the side wall portion of the second multilayer structure.
According to a tenth aspect of the present invention, a semiconductor device comprises a substrate, a multilayer structure of a gate insulator film and a gate electrode stacked in this order selectively formed on a main surface of the substrate, a side wall, formed on a side wall portion of the multilayer structure, consisting of at least first and second materials and having an exposure region exposing the second material between a portion of an upper surface of the side wall exposing the first material and an upper surface of the multilayer structure, and a conductive layer formed to extend from the exposure region to the upper surface of the multilayer structure.
According to the tenth aspect of the present invention, the width of the conductive layer is larger than that of the gate electrode. Thus, reduction of gate resistance can be attained.
According to an eleventh aspect of the present invention, the side wall according to the tenth aspect consists of the first and second materials and a third material, the upper surface of the side wall has a portion exposing the third material between the exposure region and the upper surface of the multilayer structure, and the conductive layer is a semiconductor-metal compound formed by the reaction of a semiconductor growth layer with metal, the semiconductor growth layer being formed by growing a semiconductor from each of the exposure region and the upper surface of the multilayer structure to extend from the exposure region to the upper surface of the multilayer structure through growth to the direction of the gate length.
According to the eleventh aspect of the present invention, the semiconductor growth layer extending from the exposure region to the upper surface of the multilayer structure is formed through growth to the direction of the gate length and this semiconductor growth layer reacts with the metal to form the semiconductor-metal compound, whereby a conductive layer having a larger width than the gate electrode can be properly formed.
According to a twelfth aspect of the present invention, a semiconductor device comprises a substrate, a multilayer structure of a gate insulator film and a gate electrode stacked in this order selectively formed on a main surface of the substrate, a side wall, formed on a side wall portion of the multilayer structure, consisting of at least first and second materials and having a first region exposing the second material on a side surface of the side wall in the vicinity of the main surface of the substrate, and a conductive layer consisting of a semiconductor-metal compound formed by the reaction of a semiconductor growth layer with metal, the semiconductor growth layer being formed by growing a semiconductor from each of the first region and the exposed main surface of the substrate.
According to the twelfth aspect of the present invention, the semiconductor growth layer is formed by growing the semiconductor not only from the exposed main surface of the substrate but also from the first region of the side wall. Therefore, occurrence of a facet can be avoided on an end portion of the semiconductor growth layer closer to the gate electrode.
According to a thirteenth aspect of the present invention, the semiconductor device according to the twelfth aspect of the present invention further comprises an element isolation structure, formed on an element isolation region of the substrate, having a projecting part at least partially projecting on the main surface of the substrate, and a second region consisting of a third material formed on a side wall portion of the projecting part, and the semiconductor growth layer is formed by growing a semiconductor from each of the first region, the exposed main surface of the substrate and the second region.
According to the thirteenth aspect of the present invention, the semiconductor growth layer is formed by growing the semiconductor from each of the exposed main surface of the substrate, the first region of the side wall and the second region formed on the side wall portion of the projecting part of the element isolation structure. Therefore, occurrence of a facet can be avoided on an end portion of the semiconductor growth layer closer to the element isolation structure. Thus, a source/drain region can be shallowly formed in the substrate, thereby obtaining a refined semiconductor device.
According to a fourteenth aspect of the present invention, a semiconductor device comprises a substrate, a multilayer structure of a gate insulator film and a gate electrode stacked in this order selectively formed on a main surface of the substrate, a side wall, formed on a side wall portion of the multilayer structure, consisting of at least first and second materials and having a first region exposing the second material between a portion of an upper surface of the side wall exposing the first material and an upper surface of the multilayer structure while having a second region exposing the second material in a side surface of the side wall in the vicinity of the main surface of the substrate, a first conductive layer consisting of a first semiconductor-metal compound formed by the reaction of a first semiconductor growth layer with metal, the first semiconductor growth layer being formed by growing a semiconductor from each of the first region and the upper surface of the multilayer structure to extend from the first region to the upper surface of the multilayer structure through growth to the direction of the gate length, and a second conductive layer consisting of a second semiconductor metal compound formed by the reaction of a second semiconductor growth layer with metal, the second semiconductor growth layer being formed by growing a semiconductor from each of the second region and the exposed main surface of the substrate.
According to the fourteenth aspect of the present invention, gate resistance can be reduced without increasing the width of the gate electrode in relation to the semiconductor device having a salicide structure while occurrence of a facet can be avoided on an end portion of the second semiconductor growth layer closer to the gate electrode.
According to a fifteenth aspect of the present invention, the semiconductor device according to the fourteenth aspect of the present invention further comprises an element isolation structure, formed on an element isolation region of the substrate, having a projecting part at least partially projecting on the main surface of the substrate, and a third region consisting of a third material formed on a side wall portion of the projecting part, and the second semiconductor growth layer is formed by growing the semiconductor from each of the second region, the exposed main surface of the substrate and the third region.
According to the fifteenth aspect of the present invention, gate resistance can be reduced without increasing the width of the gate electrode in relation to the semiconductor device having a salicide structure while occurrence of a facet can be avoided on an end portion of the second semiconductor growth layer closer to the gate electrode and occurrence of a facet can be avoided also on an end portion of the semiconductor growth layer closer to the element isolation structure. Therefore, a source/drain region can be shallowly formed in the substrate, and a refined semiconductor device can be obtained.
According to a sixteenth aspect of the present invention, a semiconductor device comprises a substrate having a first element forming region for forming a first semiconductor element and a second element forming region for forming a second semiconductor element, a first multilayer structure of a gate insulator film and a gate electrode stacked in this order selectively formed on a main surface of the substrate in the first element forming region, a second multilayer structure of a gate insulator film and a gate electrode stacked in this order selectively formed on a main surface of the substrate in the second element forming region, a first side wall having a first width formed on a side wall portion of the first multilayer structure, a second side wall having a second width different from the first width formed on a side wall portion of the second multilayer structure, paired first impurity implantation regions formed by implanting an impurity into the main surface of the substrate in the first element forming region through the first multilayer structure and the first side wall serving as masks and paired second impurity implantation regions formed by implanting an impurity into the main surface of the substrate in the second element forming region through the second multilayer structure and the second side wall serving as masks.
According to the sixteenth aspect of the present invention, the first and second impurity regions are formed by implanting the impurity through the first and second multilayer structures and the first and second side walls serving as masks respectively, while the widths of the first and second side walls are different from each other. Therefore, the distance between the paired first impurity implantation regions and that between the paired second impurity implantation regions can be set independently of each other in response to the respective applications of the first and second semiconductor elements.
According to a seventeenth aspect of the present invention, the first side wall consists of at least first and second materials and has an exposure region exposing the second material between a portion of an upper surface of the first side wall exposing the first material and an upper surface of the first multilayer structure in the semiconductor device according to the sixteenth aspect of the present invention, and the semiconductor device further comprises a conductive layer formed to extend from the exposure region to the upper surface of the first multilayer structure.
According to the seventeenth aspect of the present invention, gate resistance of the first semiconductor element can be reduced without increasing the width of the gate electrode in the first multilayer structure.
According to an eighteenth aspect of the present invention, the second side wall is formed by removing the first material from the first side wall formed on a side wall portion of the second multilayer structure in the semiconductor device according to the seventeenth aspect of the present invention.
According to the eighteenth aspect of the present invention, the second side wall having a width shorter than the first side wall by the width of the first material can be formed on the side wall portion of the second multilayer structure.
A first object of the present invention is to obtain a method of manufacturing a semiconductor device which can reduce gate resistance by increasing the width of a conductive layer formed on a gate electrode without increasing the gate length in relation to a MOSFET having a salicide structure, and to obtain a method of manufacturing a semiconductor device suitable for refinement which enables formation of a shallow source/drain region by preventing a conductive layer formed on the source/drain region of a substrate from reaching a deep portion of the substrate. A second object of the present invention is to obtain a method of manufacturing a semiconductor device which can set distances between impurity regions of source parts and those in drain parts independently of each other in response to required performance in relation to a semiconductor device having a plurality of types of semiconductor elements for different applications formed in a single wafer.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.